The present invention relates to DC offset calibration circuits, and more particularly, to a low-noise DC offset calibration circuit and related receiver stage.
In wireless receiver design, because overall gain of the wireless receiver is very high, even slight process variations can cause a large DC offset at an output of the wireless receiver. Dynamic range of the output, which is passed to a baseband circuit, is thereby reduced.
A wireless receiver 10, shown in FIG. 1, includes a low noise amplifier (LNA) 100, a mixer 110, a channel-select filter 120, and a programmable gain amplifier (PGA) 130. To reduce DC offset of the wireless receiver 10, a DC offset calibration circuit 140 may be used to perform DC offset compensation. The DC offset calibration circuit 140 includes a number of switched current sources 141, which may be coupled to an input end of an operational amplifier 131 of the PGA 130, as shown in FIG. 2. A DC offset compensation voltage is then generated across feedback resistors Rfb. DC offset calibration resolution is determined by sizes of the switched current sources. In order to provide better resolution, transistors utilized for realizing the switched current sources are relatively small, which leads to a large contribution of flicker noise.